NASA and Microchip Launch Next-Generation Space Processor

The High-Performance Spaceflight Computing (HPSC) processor promises a 500x performance leap over current radiation-hardened chips.

"Building on the legacy of previous space processors, this new multicore system is fault-tolerant, flexible, and extremely high-performing."
— Eugene Schwanbeck, NASA Game Changing Development program

A Leap in Space Computing

NASA, in partnership with Microchip Technology Inc., has developed a new radiation-hardened system-on-chip (SoC) called the High-Performance Spaceflight Computing (HPSC) processor. The project aims to deliver a dramatic increase in computational capability for space missions while simultaneously reducing system cost and power consumption.

Testing of the processor began in February 2024 at NASA's Jet Propulsion Laboratory (JPL).

Processor Development and Architecture

The HPSC processor is a system-on-a-chip (SoC) that integrates central processing units, computational offloads, networking units, memory, and input/output interfaces into a single device. Its scalable architecture allows unused functions to power down for improved energy efficiency.

Two Versions for Different Missions

The processor family includes two distinct versions:

• Radiation-hardened version: Designed for deep-space and long-duration missions, including travel to the Moon and Mars.
• Radiation-tolerant version: Designed for low Earth orbit satellites.

The technology uses advanced Ethernet for connecting sensors or clustering chips, enabling onboard processing of large data volumes for real-time autonomous decisions.

Testing and Performance

Testing of the HPSC processor began in February 2024 at NASA's Jet Propulsion Laboratory and is expected to continue for several months. Tests include radiation, thermal, and shock evaluations, as well as functional performance assessments.

"We are putting these new chips through the wringer by carrying out radiation, thermal, and shock tests while also evaluating their performance through a rigorous functional test campaign."
— Jim Butler, HPSC project manager at JPL

High-fidelity landing scenarios from real NASA missions are being used to simulate real-world performance. Initial results indicate the processor is operating at 500 times the performance of current radiation-hardened chips.

Project Management and Partners

The HPSC project is a public-private partnership led by NASA's Space Technology Mission Directorate's Game Changing Development (GCD) program, based at NASA's Langley Research Center and the Jet Propulsion Laboratory.

Microchip Technology Inc. was selected as a partner in 2022 and funded its own research and development. Samples have already been provided to early access partners in the defense and commercial aerospace industries.

Applications

The processor is designed to enable a wide range of future missions:

• Enable autonomous spacecraft to use artificial intelligence for real-time responses
• Support deep space missions in analyzing and transmitting data
• Assist future human missions to the Moon and Mars

Once certified, NASA plans to incorporate the chip into Earth orbiters, rovers, crewed habitats, and deep-space missions. Microchip also plans to adapt the technology for terrestrial industries, including automotive, aviation, consumer electronics, industrial systems, and aerospace.

Background

Space computing technology has evolved significantly since the Apollo Guidance Computers of the 1960s. Radiation-hardened processors have been used for decades in NASA missions, including Mars rovers, orbiters, capsules, and space telescopes. The HPSC project responds to the increased complexity and duration of future missions requiring greater computing power, autonomy, and resilience.